1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to an analog sampling apparatus of a liquid crystal display device for sufficiently securing a sampling time and a data driving time.
2. Discussion of the Related Art
A liquid crystal display device controls the light transmittance of liquid crystal cells in accordance with a video signal, to display a picture.
In a typical active matrix type liquid crystal display device, active switching devices are used to control the electric fields in each liquid crystal cell to control the light transmittance of the cell. By controlling the active switching devices, moving images can be displayed. A thin film transistor (hereinafter, referred to as ‘TFT’) is the device primarily used for switching devices in the active matrix type liquid crystal display device.
A liquid crystal display device of the related art, as shown in FIG. 1, includes a liquid crystal display panel 2 having a plurality of data lines 5 crossing a plurality of gate lines 6 and TFTs for driving liquid crystal cells formed at the crossings of the gate and data lines; a data driver 3 for supplying data to the data lines 5; a gate driver 4 for supplying a scan pulse to the gate lines 6; and a timing controller 1 for controlling the data driver 3 and the gate driver 4.
The liquid crystal display panel 2 includes liquid crystal injected between two glass substrates. The data lines 5, gate lines 6 and TFTs are formed on a lower of the two glass substrates. The TFTs supply the data from the data lines 5 to the liquid crystal cell in response to the scan pulse from the gate lines 6. To this end, a gate electrode of the TFT is connected to the gate line 6, a source electrode is connected to the data line 5, and a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc. Further, a storage capacitor Cst for maintaining the voltage of the liquid crystal cell is formed on the lower glass substrate of the liquid crystal display panel.
The timing controller 1 receives digital video data RGB, a horizontal synchronization signal H, a vertical synchronization signal V, and a clock signal CLK and generates a gate control signal GDC for controlling the gate driver 4 and a data control signal DDC for controlling the data driver 3. Further, the timing controller 1 supplies the digital video data RGB to the data driver 3.
The gate driver 4 includes a shift register for sequentially generating a scan pulse in response to the gate control signal GDC from the timing controller 1; a level shifter for shifting a swing width of the scan pulse to a level that is suitable for driving the liquid crystal cell Clc; an output buffer, etc. The gate driver 4 supplies the scan pulse to the gate line 6 to turn on the TFTs connected to the gate line 6, thereby selecting the liquid crystal cells Clc of one horizontal line to which a pixel voltage, i.e., analog gamma compensation voltage, of the data is to be supplied. The data generated by the data driver 3 is supplied to the liquid crystal cell Clc of the horizontal line that is selected by the scan pulse.
The data driver 3 supplies the data to the data lines 5 in response to the data drive control signal DDC supplied from the timing controller 1. The data driver 3 samples the digital data RGB from the timing controller 1, latches the data, and then converts the data into an analog gamma voltage. The data driver 3 may be realized as a plurality of data integrated circuits (hereinafter, referred to as ‘ICs’) each having a configuration as shown in FIG. 2.
Each of the data ICs 3A, as shown in FIG. 2, includes a data register 21 that receives the digital data RGB from the timing controller 1; a shift register 22 for generating a sampling clock; a first latch 23, a second latch 24, and a digital/analog converter (hereinafter, referred to as ‘DAC’) 25 that are connected between the shift register 22 and an output circuit 26 by k (where k is an integer smaller than m, the number of data lines of the liquid crystal display panel) number of data lines DL1 to DLk; and a gamma voltage supplier 27 connected between the gamma reference voltage generator 4 and a DAC 25.
The data register 21 supplies the digital data RGB from the timing controller 1 to the first latch 23. The shift register 22 shifts a source start pulse from the timing controller 1 in accordance with a source sampling clock signal SSC to generate a sampling signal. Further, the shift register 22 shifts a source start pulse SSP to transmit a carry signal CAR to the shift register 22 of the next stage. The first latch 23 sequentially samples the digital data RGB from the data register 21 in response to the sampling signal that is sequentially supplied by the shift register 22. The second latch 24 latches the data supplied from the first latch 23, and then simultaneously outputs the latched data in response to a source output enable signal SOE from the timing controller 1. The DAC 25 converts the data from the second latch 24 into a gamma voltage DGH, DGL from the gamma voltage supplier 27. The gamma voltage DGH, DGL is an analog voltage that corresponds to each of the gray levels of the digital input data. The output circuit 26 includes a buffer connected to each of the data lines. The gamma voltage supplier 27 subdivides the gamma reference voltage inputted from the gamma reference voltage generator 4 to supply the gamma voltage corresponding to each gray level to the DAC 25.
The data drive circuit has a complicated circuit configuration, and the circuitry of the data drive circuit occupies a large area, making embedding the data drive circuitry on the substrate of the liquid crystal display panel difficult.
An analog sampling type liquid crystal display device has been proposed as a solution. As shown in FIG. 3, a analog sampling type liquid crystal display device of the related art includes common bus lines 201 to 240 connected to an output terminal of the data register 21 in a one-to-one relationship, with a channel selecting part 34 and a sampling & holding part 33 disposed between the common bus lines 201 to 240 and the data lines DL1 to DL42. A plurality of data output bus lines are connected to each of the common bus lines 201 to 240. For example, the first and 41st data output bus lines 301 and 341 are connected to the first common bus line 201. The channel selecting part 34 includes a plurality of switch devices 34A that are connected to the data output bus lines 301 in the one-to-one relationship. The switch devices 34A for the channel selecting part 34 may be implemented using CMOS technology and are sequentially turned on in response to a control signal from the shift register 32, thereby acting to supply the data from the data output bus lines 301 to the sampling & holding part 33. The sampling & holding part 33 sequentially samples and holds the data from the channel selecting part 34, and then supplies the held data to the data lines DL1 to DL42 simultaneously.
However, in the analog sampling method of the related art, the time available for sampling the data in the sampling & holding part 34 and supplying the data voltage to the data lines is too short to supply the desired voltages to the liquid crystal cells.